As Vice President of Asia
Pacific design centers at Cypress Semiconductor, Nagendra
presently manages a 150-engineer team across four design
centers in the US, India & China. Current responsibilities
include delivering on chip commitments to customers and
managing the teams to success. His key contributions include
starting two design centers for Cypress in India and China,
and promoting Cypress brand via keynote, panels, press conferences
and articles. Nagendra has held various technical and managerial
positions at AT&T Bell Laboratories, Cadence Design
Systems and Silicon Value, a fabless ASIC startup in Silicon
Valley. He has 21+ years of experience in chip design and
software development, backed by a Ph.D. in Computer Science
from IIT, Chicago. His areas of interest are verification,
both formal and informal, and chip integration that includes
synthesis, place & route and design closure.
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